Low-energy and fast spiking neural network for context-dependent learning on FPGA
Asgari, Hajar, Mazloom-Nezhad Maybodi, Babak, Payvand, Melika, and Rahimi Azghadi, Mostafa (2020) Low-energy and fast spiking neural network for context-dependent learning on FPGA. IEEE Transactions on Circuits and Systems Part 2: express briefs, 67 (11). pp. 2697-2701.
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Abstract
Supervised, unsupervised, and reinforcement learning (RL) mechanisms are known as the most powerful learning paradigms empowering neuromorphic systems. These systems typically take advantage of unsupervised learning because they can learn the distribution of sensory information. However, to perform a task, not only is it important to have sensory information, but also it is required to have information about the context in which the system is operating. In this sense, reinforcement learning is very powerful for interacting with the environment while performing a context-dependent task. The predominant motivation for this research is to present a digital architecture for a spiking neural network (SNN) model with RL capability suitable for learning a context-dependent task. The proposed architecture is composed of hardware-friendly leaky integrate-and-firing (LIF) neurons and spike timing dependent plasticity (STDP)-based synapses implemented on a field programmable gate array (FPGA). Hardware synthesis and physical implementations show that the resulting circuits can faithfully reproduce the outcome of a learning task previously performed in both animal experimentation and computational modelings. Compared to the state-of-the-art neuromorphic FPGA circuits with context-dependent learning capability, our circuit fires 10.7 times fewer spikes, which accelerates learning 15 times, while requiring 16 times less energy. This is a significant step in achieving fast and low-energy SNNs with context-dependent learning ability on FPGAs.
Item ID: | 62458 |
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Item Type: | Article (Research - C1) |
ISSN: | 1558-3791 |
Keywords: | neuromorphic engineering, field programmablegate array (FPGA), context-dependent task |
Copyright Information: | (C) 2019 IEEE. |
Date Deposited: | 11 Mar 2020 02:11 |
FoR Codes: | 40 ENGINEERING > 4008 Electrical engineering > 400801 Circuits and systems @ 100% |
SEO Codes: | 97 EXPANDING KNOWLEDGE > 970109 Expanding Knowledge in Engineering @ 50% 97 EXPANDING KNOWLEDGE > 970110 Expanding Knowledge in Technology @ 50% |
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