Novel VLSI implementation for triplet-based spike-timing dependent plasticity
Rahimiazghadi, Mostafa, Kavehei, Omid, Al-Sarawi, Said, Iannella, Nicoangelo, and Abbott, Derek (2011) Novel VLSI implementation for triplet-based spike-timing dependent plasticity. In: Proceedings of the 7th International Conference on Intelligent Sensors, Sensor Networks and Information Processing. pp. 158-162. From: ISSNIP 2011: 7th International Conference on Intelligent Sensors, Sensor Networks and Information Processing, 6-9 December 2011, Adelaide, SA, Australia.
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Abstract
Spike Timing-Dependent Plasticity (STDP) is one of several plasticity rules that is believed to play an important role in learning and memory in the brain. In conventional pair-based STDP learning, synaptic weights are altered by utilizing the temporal difference between pairs of pre- and post-synaptic spikes. This learning rule, however, fails to reproduce reported experimental measurements when using stimuli either by patterns consisting of triplet or quadruplet of spikes or increasing the repetition frequency of pairs of spikes. Significantly, a previously described spike triplet-based STDP rule succeeds in reproducing all of these experimental observations. In this paper, we present a new spike triplet-based VLSI implementation, that is based on a previous pair-based STDP circuit [1]. This implementation can reproduce similar results to those observed in various physiological STDP experiments, in contrast to traditional pair-based VLSI implementation. Simulation results using standard 0.35 μm CMOS process of the new circuit are presented and compared to published experimental data [2].
Item ID: | 45710 |
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Item Type: | Conference Item (Research - E1) |
ISBN: | 978-1-4577-0674-5 |
Funders: | Australian Research Council (ARC) |
Date Deposited: | 20 Jul 2017 04:08 |
FoR Codes: | 09 ENGINEERING > 0906 Electrical and Electronic Engineering > 090604 Microelectronics and Integrated Circuits @ 100% |
SEO Codes: | 97 EXPANDING KNOWLEDGE > 970109 Expanding Knowledge in Engineering @ 100% |
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